Area-aware RF front-end circuit design in nanometer CMOS

Scriptie/masterproef: Doctoral Thesis


Todays society relies heavily on wireless communication. More bandwidth and more flexibility is demanded which has triggered the development of flexible multistandard radios and high-bandwidth 60 GHz applications. To meet the requirements of such radios, high-speed but area-expensive downscaled CMOS is used. Inductors, used in RF building blocks, typically consume a significant part of the chip area in these radios. Their large dimensions and poor quality due to the lossy substrate makes their application rather unfortunate.
To lower the chip cost, this work focuses on reducing the area consumed by inductors. Three techniques are proposed to do so: inductor reuse, inductorless design and inductor miniaturization. With the first technique, when an inductor is present and unavoidable on chip, we reuse it for other purposes. As such, the functionality of the inductors is increased, and their presence on chip is revalued. With inductorless design, we aim to remove inductors from the circuits completely. As a benefit, designs scale better with the technology, and can take more advantage of the benefits of scaling. A last technique - inductor miniaturization - meets the best of both: inductors, but on a miniature area. Inductors are miniaturized, and the circuits are adapted to be compatible with these miniaturized inductors.
The proposed techniques are illustrated by means of many designs in downscaled CMOS. We show how the circuit area can be reduced up to a factor one thousand, rethinking some of the design approaches, without worsening the RF performance.
Datum Prijs27 aug 2008
BegeleiderMaarten Kuijk (Promotor), Piet Wambacq (Promotor), Yves Rolain (Jury), Rik Pintelon (Jury), Johan Stiens (Jury), Bram Nauta (Jury) & John Long (Jury)

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